Wednesday, 23 April 2014

Level 1

I've re-thought my porting strategy slightly, and decided to 'emulate' the 6502 zero-page registers using the Z80 index register (specifically, IX). This allows a more congruent line-by-line port without juggling Z80 registers with the accumulator for zero-page access; the indexed addressing instructions work with most of the Z80 registers. The only caveat is the signed offset; if I'm careful that shouldn't be an issue.

For the 6809 I'll use the DP register for the same purpose.

I've defined some macro's in the Z80 code in case the whole IX thing doesn't work out, however it's looking pretty good so far. It allows me to use (Z80) A, B & C for (6502) A, X & Y respectively for zero-page operations with a 1:1 correspondence between the code bases.

After adjusting for the above I started work on coding the level display routine(s). I've hard-coded the level 1 data in the 'disk buffer' and coded the unpack and display routine. The latter was cut-down just to get something on the screen, and after fixing a few bugs in the pixel-doubling routine which didn't reveal themselves when displaying alphanumeric characters (due to their striped nature) I was greeted with this:
Level 1 - TRS-80 Model 4

Between the convoluted 6502 code and the on-the-fly pixel-doubling, it's a bit slow but at least it looks the real deal! I'll stop at this point and bring the Coco3 (6809) code up-to-date.


  1. Wow, you've been busy. You can make zero page 'emulation' a bit faster and no larger by using HL and a page-aligned zero page. Initialize with "LD H,zeropage/256" and do each operation in two steps: "LD L,loc; operation (HL)".

  2. That's something I didn't consider - thanks, I'll look into it. The only issue may be that I'm using HL for a lot of stuff that isn't directly translatable, and those routines often access the zero page registers, so it may not be feasible for me. But very interesting that LD, L, and (HL) is actually faster than (IX+dd)!!!